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Single-Channel, 1024-Position, 1% R-Tolerance Digital Potentiometer AD5293
FEATURES
Single-channel, 1024-position resolution 20 k nominal resistance Calibrated 1% nominal resistor tolerance (resistor performance mode mode) Rheostat mode temperature coefficient: 35 ppm/C Voltage divider temperature coefficient: 5 ppm/C Single-supply operation: 9 V to 33 V Dual-supply operation: 9 V to 16.5 V SPI-compatible serial interface Wiper setting readback
FUNCTIONAL BLOCK DIAGRAM
VDD POWER-ON RESET VLOGIC SCLK SYNC DIN SERIAL INTERFACE 10 RDAC REGISTER RESET
AD5293
A W
B
SDO
APPLICATIONS
Mechanical potentiometer replacement Instrumentation: gain and offset adjustment Programmable voltage-to-current conversion Programmable filters, delays, and time constants Programmable power supply Low resolution DAC replacement Sensor calibration
RDY VSS EXT_CAP GND
07675-001
Figure 1.
GENERAL DESCRIPTION
The AD5293 is a single-channel, 1024-position digital potentiometer1 with <1% end-to-end resistor tolerance error. The AD5293 performs the same electronic adjustment function as a mechanical potentiometer with enhanced resolution, solid state reliability, and superior low temperature coefficient performance. This device is capable of operating at high voltages and supporting both dual-supply operation at 10.5 V to 15 V and single-supply operation at 21 V to 30 V.
1
The AD5293 offers guaranteed industry-leading low resistor tolerance errors of 1% with a nominal temperature coefficient of 35 ppm/C. The low resistor tolerance feature simplifies open-loop applications as well as precision calibration and tolerance matching applications. The AD5293 is available in a compact 14-lead TSSOP package. The part is guaranteed to operate over the extended industrial temperature range of -40C to +105C.
In this data sheet, the terms digital potentiometer and RDAC are used interchangeably.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved.
AD5293 TABLE OF CONTENTS
Features ...............................................................................................1 Applications ........................................................................................1 Functional Block Diagram ...............................................................1 General Description ..........................................................................1 Revision History ................................................................................2 Specifications......................................................................................3 Electrical Characteristics ..............................................................3 Resistor Performance (R-PERF) Mode Code Range ................4 Interface Timing Specifications ...................................................5 Timing Diagrams...........................................................................6 Absolute Maximum Ratings.............................................................7 Thermal Resistance .......................................................................7 ESD Caution ...................................................................................7 Pin Configuration and Function Descriptions ..............................8 Typical Performance Characteristics ..............................................9 Test Circuits ..................................................................................... 13 Theory of Operation ...................................................................... 14 Serial Data Interface ................................................................... 14 Shift Register ............................................................................... 14 RDAC Register ............................................................................ 14 Write Protection ......................................................................... 14 Basic Operation .......................................................................... 14 Shutdown Mode.......................................................................... 14 Reset ............................................................................................. 15 Resistor Performance Mode ...................................................... 15 Daisy-Chain Operation ............................................................. 15 RDAC Architecture .................................................................... 16 Programming the Variable Resistor ......................................... 16 Programming the Potentiometer Divider ............................... 16 EXT_CAP Capacitor .................................................................. 17 Terminal Voltage Operating Range.......................................... 17 Applications Information .............................................................. 18 High Voltage DAC ...................................................................... 18 Programmable Voltage Source with Boosted Output............ 18 High Accuracy DAC .................................................................. 18 Audio Volume Control .............................................................. 19 Outline Dimensions ....................................................................... 20 Ordering Guide........................................................................... 20
REVISION HISTORY
4/09--Revision 0: Initial Version
Rev. 0 | Page 2 of 20
AD5293 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VDD = 21 V to 33 V, VSS = 0 V; VDD = 10.5 V to 16.5 V, VSS = -10.5 V to -16.5 V; VLOGIC = 2.7 V to 5.5 V, VA = VDD, VB = VSS, -40C < TA < +105C, unless otherwise noted. Table 1.
Parameter DC CHARACTERISTICS, RHEOSTAT MODE Resolution Resistor Differential Nonlinearity 2 Resistor Integral Nonlinearity2 Nominal Resistor Tolerance (R-Perf Mode) 3 Nominal Resistor Tolerance (Normal Mode) Resistance Temperature Coefficient 4 Wiper Resistance DC CHARACTERISTICS, POTENTIOMETER DIVIDER MODE Resolution Differential Nonlinearity 5 Integral Nonlinearity5 Voltage Divider Temperature Coefficient4 Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Terminal Voltage Range 6 Capacitance A, Capacitance B4 Capacitance W4 Common-Mode Leakage Current DIGITAL INPUTS Input Logic High Input Logic Low Input Current Input Capacitance4 DIGITAL OUTPUTS (SDO and RDY) Output High Voltage Output Low Voltage Tristate Leakage Current Output Capacitance4 POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Positive Supply Current Negative Supply Current Logic Supply Range Logic Supply Current Power Dissipation 7 Power Supply Rejection Ratio4 Symbol Conditions Min Typ 1 Max Unit
N R-DNL R-INL R-INL RAB/RAB RAB/RAB (RAB/RAB)/T x 106 RW
RWB |VDD - VSS | = 26 V to 33 V |VDD - VSS | = 21 V to 26 V See Table 2
10 -1 -2 -3 -1
0.5 20 35 60
+1 +2 +3 +1
Bits LSB LSB LSB % % ppm/C
100
N DNL INL (VW/VW)/T x 106 VWFSE VWZSE VA, VB, VW CA, CB CW ICM VIH VIL IIL CIL VOH VOL COL VDD VDD/VSS IDD ISS VLOGIC ILOGIC PDISS PSSR
10 -1 -1.5 Code = half scale Code = full scale Code = zero scale -8 0 VSS f = 1 MHz, measured to GND, code = half-scale f = 1 MHz, measured to GND, code = half-scale VA = VB = VW VLOGIC = 2.7 V to 5.5 V VLOGIC = 2.7 V to 5.5 V VIN = 0 V or VLOGIC 2.0 50 65 5
+1 +1.5
Bits LSB LSB ppm/C LSB LSB V pF pF nA V V A pF V V A pF V V A A V A W %/%
0 8 VDD
1 JEDEC compliant 0.8 1 5
RPULL_UP = 2.2 k to VLOGIC RPULL_UP = 2.2 k to VLOGIC
VLOGIC - 0.4 -1 5 GND + 0.4 +1
VSS = 0 V VDD/VSS = 16.5 V VDD/VSS = 16.5 V VLOGIC = 5 V; VIH = 5 V, or VIL = GND VIH = 5 V, or VIL = GND VDD/VSS = 15 V 10%
9 9 -2 2.7 0.1 -0.1 1 8 0.025
33 16.5 2 5.5 10 110 0.08
Rev. 0 | Page 3 of 20
AD5293
Parameter DYNAMIC CHARACTERISTICS4, 8 Bandwidth Total Harmonic Distortion VW Settling Time Symbol BW THDW tS Conditions -3 dB VA = 1 V rms, VB = 0 V, f = 1 kHz, VA = 30 V, VB = 0 V, 0.5 LSB error band, initial code = zero scale Code = full scale, normal mode Code = full scale, R-Perf mode Code = half scale, normal mode Code = half scale, R-Perf mode RWB = 10 k, TA = 25C, 0 kHz to 200 kHz Min Typ 1 520 -93 Max Unit kHz dB
Resistor Noise Density
1 2
eN_WB
750 2.5 2.5 5 0.11
ns s s s nV/Hz
Typicals represent average readings at 25C; VDD = +15 V, VSS = -15 V, and VLOGIC = 5 V. Resistor position nonlinearity error. R-INL is the deviation from an ideal value measured between the RWB at Code 0x02 and the RWB at Code 0xFF or between RWA at Code 0xFD and RWA at Code 0x00. R-DNL measures the relative step change from ideal between successive tap positions. The specification is guaranteed in resistor performance mode with a wiper current of 1 mA for VA < 12 V and 1.2 mA for VA 12 V. 3 The terms resistor performance mode and R-Perf mode are used interchangeably. 4 Guaranteed by design; not subject to production test. 5 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. 6 The A, B, and W resistor terminals have no limitations on polarity with respect to each other. Dual-supply operation enables ground-referenced bipolar signal adjustment. 7 PDISS is calculated from (IDD x VDD) + (ISS x VSS) + (ILOGIC x VLOGIC). 8 All dynamic characteristics use VDD = +15 V, VSS = -15 V, and VLOGIC = 5 V.
RESISTOR PERFORMANCE (R-PERF) MODE CODE RANGE
Table 2.
Resistor Tolerance per Code 1% R-Tolerance 2% R-Tolerance 3% R-Tolerance |VDD - VSS| = 30 V to 33 V RWB From 0x15E to 0x3FF From 0x8C to 0x3FF From 0x5A to 0x3FF RWA From 0x00 to 0x2A1 From 0x00 to 0x373 From 0x00 to 0x3A5 |VDD - VSS| = 26 V to 30 V RWB From 0x1F4 to 0x3FF From 0xB4 to 0x3FF From 0x64 to 0x3FF RWA From 0x00 to 0x20B From 0x00 to 0x34B From 0x00 to 0x39B |VDD - VSS| = 22 V to 26 V RWB From 0x1F4 to 0x3FF From 0xFA to 0x3FF From 0x78 to 0x3FF RWA From 0x00 to 0x20B From 0x00 to 0x305 From 0x00 to 0x387 |VDD - VSS| = 21 V to 22 V RWB N/A From 0xFA to 0x3FF From 0x78 to 0x3FF RWA N/A From 0x00 to 0x305 From 0x00 to 0x387
Rev. 0 | Page 4 of 20
AD5293
INTERFACE TIMING SPECIFICATIONS
VDD = VSS = 15 V, VLOGIC = 2.7 V to 5.5 V, and -40C < TA < +105C. All specifications TMIN to TMAX, unless otherwise noted. Table 3.
Parameter t1 2 t2 t3 t4 t5 t6 t7 t8 t9 t10 4 t114 t124 Limit 1 20 10 10 10 5 5 1 400 3 14 1 40 2.4 410 1.5 450 450 20 2 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max s max ns max ms max ns max ns max ns min ms max Test Conditions/Comments SCLK cycle time SCLK high time SCLK low time SYNC to SCLK falling edge setup time Data setup time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time SYNC rising edge to next SCLK falling edge ignore RDY rise to SYNC falling edge SYNC rise to RDY fall time RDY low time, RDAC register write command execute time (R-Perf mode) RDY low time, RDAC register write command execute time (normal mode) Software\hardware reset RDY low time, RDAC register read command execute time SCLK rising edge to SDO valid Minimum RESET pulse width (asynchronous) Power-on time to half scale
t134 t144 tRESET tPOWER-UP 5
1 2
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Maximum SCLK frequency = 50 MHz. 3 Refer to t12 and t13 for RDAC register command operations. 4 RPULL_UP = 2.2 k to VLOGIC with a capacitance load of 168 pF. 5 Typical power supply voltage slew rate of 2 ms/V.
DB9 (MSB) 0 0 C3 C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 DB0 (LSB) D1 D0
07675-002
CONTROL BITS
DATA BITS
Figure 2. Shift Register Contents
Rev. 0 | Page 5 of 20
AD5293
TIMING DIAGRAMS
t4
SCLK SYNC
t2 t3
t1
t7 t9
t8
t5 t6
DIN X X C3 C2 D7 D6 D2 D1 D0
SDO
t10
RDY RESET
t11
t12
07675-003
tRESET
Figure 3. Write Timing Diagram
SCLK
t9
SYNC
DIN
X
X
C3
D0
D0
X
X
C3
D1
D0
t14
SDO X X C3 D1 D0
07675-004
t11
RDY
t13
Figure 4. Read Timing Diagram
Rev. 0 | Page 6 of 20
AD5293 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 4
Parameter VDD to GND VSS to GND VLOGIC to GND VDD to VSS VA, VB, VW to GND IA, IB, IW Pulsed 1 Frequency >10 kHz Frequency 10 kHz Continuous Digital Input and Output Voltage to GND EXT_CAP Voltage to GND Operating Temperature Range Maximum Junction Temperature (TJ max) Storage Temperature Range Reflow Soldering Peak Temperature Time at Peak Temperature Package Power Dissipation
1
Rating -0.3 V to +35 V +0.3 V to -16.5 V -0.3 V to +7 V 35 V VSS - 0.3 V, VDD + 0.3 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
3 mA/d 3 mA/d2 3 mA -0.3 V to VLOGIC +0.3 V -0.3 V to +7 V -40C to +105C 150C -65C to +150C 260C 20 sec to 40 sec (TJ max - TA)/JA
2
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 5. Thermal Resistance
Package Type 14-Lead TSSOP
1
JA 931
JC 20
Unit C/W
JEDEC 2s2p test board, still air (from 0 m/sec to 1 m/sec of airflow).
ESD CAUTION
Maximum terminal current is bounded by the maximum current handling of the switches, the maximum power dissipation of the package, and the maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 d = pulse duty factor.
Rev. 0 | Page 7 of 20
AD5293 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RESET 1 VSS 2 A3 W4 B5 VDD 6 EXT_CAP 7
14 RDY 13 SDO
AD5293
TOP VIEW Not to Scale
12 SYNC 11 SCLK 10 DIN
07675-005
9 8
GND VLOGIC
Figure 5. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 Mnemonic RESET VSS A W B VDD EXT_CAP VLOGIC GND DIN SCLK SYNC Description Hardware Reset. Sets the RDAC register to midscale. RESET is activated at the logic high transition. Tie RESET to VLOGIC if not used. Negative Supply. Connect to 0 V for single-supply applications. This pin should be decoupled with 0.1 F ceramic capacitors and 10 F capacitors. Terminal A of RDAC. VSS VA VDD. Wiper Terminal W of RDAC. VSS VW VDD. Terminal B of RDAC. VSS VB VDD. Positive Power Supply. This pin should be decoupled with 0.1 F ceramic capacitors and 10 F capacitors. Connect a 1 F capacitor to EXT_CAP. This capacitor must have a voltage rating of 7 V. Logic Power Supply, 2.7 V to 5.5 V. This pin should be decoupled with 0.1 F ceramic capacitors and 10 F capacitors. Ground, Logic Ground Reference. Serial Data Input. This part has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC goes low, it enables the shift register, and data is transferred in on the falling edges of the following clocks. The selected register is updated on the rising edge of SYNC, following the 16th clock cycle. If SYNC is taken high before the 16th clock cycle, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC. Serial Data Output. This open-drain output requires an external pull-up resistor. SDO can be used to clock data from the serial register in daisy-chain mode or in readback mode. Ready. This active-high, open-drain output identifies the completion of a write or read operation to or from the RDAC register.
13 14
SDO RDY
Rev. 0 | Page 8 of 20
AD5293 TYPICAL PERFORMANCE CHARACTERISTICS
1.0 0.8 0.6 0.4
DNL (LSB) INL (LSB)
-40C +25C +105C
0.15 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20 0 128 -40C 256 384 +25C 512 640 +105C 768 896 1024
07675-011 07675-015 07675-014
0.2 0 -0.2 -0.4 -0.6 -0.8 0 128 256 384 512 640 768 896 1024
07675-106
-1.0 CODE (Decimal)
CODE (Decimal)
Figure 6. R-INL in R-Perf Mode vs. Code vs. Temperature
0.6 0.5
Figure 9. R-DNL in Normal Mode vs. Code vs. Temperature
1.5
1.0 0.4 0.3
DNL (LSB)
0.5
INL (LSB)
0.2 0.1 0 -0.1
0
-0.5
-1.0 -0.2
07675-007
-0.3 0 128
-40C 256 384
+25C 512 640
+105C 768 896 1024
-1.5 0 128
-40C 256 384
+25C 512 640
+105C 768 896 1024
CODE (Decimal)
CODE (Decimal)
Figure 7. R-DNL in R-Perf Mode vs. Code vs. Temperature
1.0 0.8 0.6 0.4
INL (LSB)
Figure 10. INL in R-Perf Mode vs. Code vs. Temperature
0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1
0.2 0 -0.2 -0.4 -0.6 0 128 -40C 256 384 +25C 512 640 +105C
07675-010
DNL (LSB)
-0.2 0 128
-40C 256 384
+25C 512 640
+105C 768 896 1024
768
896
1024
CODE (Decimal)
CODE (Decimal)
Figure 8. R-INL in Normal Mode vs. Code vs. Temperature
Figure 11. DNL in R-Perf Mode vs. Code vs. Temperature
Rev. 0 | Page 9 of 20
AD5293
0.8 0.6 0.4 0.2
INL (LSB) RHEOSTAT MODE TEMPCO (ppm/C)
-40C +25C +105C
700 600 500 400 300 200 100 0
VDD = 30V, VSS = 0V
0 -0.2 -0.4 -0.6 -0.8 0 128 256 384 512 640 768 896 1024 CODE (Decimal)
07675-018
0
256
512 CODE (Decimal)
768
1024
Figure 12. INL in Normal Mode vs. Code vs. Temperature
0.10
700
POTENTIOMETER MODE TEMPCO (ppm/C)
Figure 15. Rheostat Mode Tempco RWB/T vs. Code
VDD = 30V, VSS = 0V
0.05
-40C +25C +105C
600 500 400 300 200 100 0
0
DNL (LSB)
-0.05
-0.10
-0.15
0
128
256
384
512
640
768
896
1024
07675-019
0
256
512 CODE (Decimal)
768
1024
CODE (Decimal)
Figure 13. DNL in Normal Mode vs. Code vs. Temperature
450 400 350 VDD/VSS = 15V VLOGIC = +5V ILOGIC
Figure 16. Potentiometer Mode Tempco RWB/T vs. Code
0 -4 -8 -12 -18
GAIN (dB)
0x100 0x200
SUPPLY CURRENT (nA)
300 250 200 150 100 50 0
07675-022
0x080 0x040 0x020 0x010 0x008 0x004 0x002 0x001
07675-025
-24 -28 -32 -36 -40 -44 -50 -54 1
IDD
-50 -40 -30 -20 -10 0
ISS 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (C)
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 14. Supply Current vs. Temperature
Figure 17. 20 k Gain vs. Frequency vs. Code
Rev. 0 | Page 10 of 20
07675-023
-0.20
07675-024
AD5293
68 64 60 56 52 48
PSRR (dB)
8 7 VDD/VSS = 30V/0V VA = VDD VB = VSS
THEORETICAL IWB_MAX (mA)
VDD/VSS = 15V CODE = HALF SCALE VLOGIC = +5V 0.1 1 10 100 1k 10k 100k 1M
07675-026
6 5 4 3 2 1 0 0 256 512 CODE (Decimal) 768 1024
44 40 36 32 28 24 20 16 12
FREQUENCY (Hz)
Figure 18. Power Supply Rejection Ratio vs. Frequency
-66 -68 -70 VDD/VSS = 15V CODE = HALF SCALE VIN = 1V rms
1.0 0.9
Figure 21. Theoretical Maximum Current vs. Code
VDD = 15V
SUPPLY CURRENT I LOGIC (mA)
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1
THD + N (dB)
-72 -74 -76 -78 -80
07675-027
1k
10k FREQUENCY (Hz)
100k
0
0.5
1.0
1.5 2.0 2.5 3.0 3.5 DIGITAL INPUT VOLTAGE (V)
4.0
4.5
5.0
Figure 19. Total Harmonic Distortion + Noise (THD + N) vs. Frequency
0 -10 -20 -30 VDD/VSS = 15V, CODE = HALF SCALE fIN = 1kHz
Figure 22. Supply Current, ILOGIC, vs. Digital Input Voltage
35 30 25 VWB, CODE: FULL SCALE, NORMAL MODE VWB, CODE: FULL SCALE, R-PERF MODE
THD + N (dB)
VOLTAGE (V)
20 15 10 5 0
-40 -50 -60 -70 -80
07675-028
VWB, CODE: HALF SCALE, NORMAL MODE
VWB, CODE: HALF SCALE, R-PERF MODE SYNC VDD/VSS = 30V/0V VLOGIC = 5V VA = VDD VB = VSS
07675-133
0.2
0.7
1.3
1.9
2.5
3.1
3.6
4.2
4.8
5.4
6.0
6.5
7.1
7.7
8.3
-1.0
AMPLITUDE (V)
-0.4
TIME (s)
Figure 20. THD + Noise vs. Amplitude
Figure 23. Large-Signal Settling Time, Code from Zero Scale to Full Scale
Rev. 0 | Page 11 of 20
8.9
-90 0.001
0.01
0.1
1
10
-5
07675-131
-82 100
0
07675-029
8 0.01
AD5293
1.2 1.0 0.8 0.6 VDD/VSS = 15V VLOGIC = +5V VA = VDD VB = VSS
300
VDD/VSS = 15V
250
NUMBER OF CODES
07675-135
VOLTAGE (V)
200
0.4 0.2 0 -0.2 -0.4 -0.6
150
100
50
TIME (s)
10 20 30 40 50 60 70 80 90 100 TEMPERATURE (C)
Figure 24. Maximum Transition Glitch
Figure 25. Code Range > 1% R-Tolerance Error vs. Temperature
Rev. 0 | Page 12 of 20
07675-056
-0.4 -0.2 -0.1 0.1 0.2 0.4 0.5 0.7 0.8 1.0 1.1 1.3 1.4 1.6 1.7 1.9 2.0 2.2 2.3 2.5 2.6 2.8 2.9 3.1 3.2 3.4 3.6
-0.8
0 -40 -30 -20 -10 0
AD5293 TEST CIRCUITS
Figure 26 to Figure 31 define the test conditions used in the Specifications section.
NC DUT A W B VMS
07675-030
IW
VA VDD V+ ~ B A V+ = VDD 10% VMS PSRR (dB) = 20 log V DD
07675-033
W VMS
PSS (%/%) =
VMS% VDD%
NC = NO CONNECT
Figure 26. Resistor Position Nonlinearity Error (Rheostat Operation: R-INL, R-DNL)
Figure 29. Power Supply Sensitivity (PSS, PSRR)
DUT A V+ B W
V+ = VDD 1LSB = V+/2N
A VIN OFFSET GND
07675-031
+15V W
DUT B 2.5V
OP42
VOUT
07675-036
VMS
-15V
Figure 27. Potentiometer Divider Nonlinearity Error (INL, DNL)
+15V NC
RWB = CODE = 0x00 + IWB VSS TO VDD - RW = 0.1V 0.1V IWB RWB 2
Figure 30. Gain vs. Frequency
-15V GND GND VDD DUT VSS GND A W B GND ICM +15V -15V
DUT W B
07675-032
A = NC
+15V
NC = NO CONNECT
-15V
Figure 28. Wiper Resistance
Figure 31. Common-Mode Leakage Current
Rev. 0 | Page 13 of 20
07675-037
NC
GND
AD5293 THEORY OF OPERATION
The AD5293 digital potentiometer is designed to operate as a true variable resistor for analog signals that remain within the terminal voltage range of VSS < VTERM < VDD. The patented 1% resistor tolerance feature helps to minimize the total RDAC resistance error, which reduces the overall system error by offering better absolute matching and improved open-loop performance. The digital potentiometer wiper position is determined by the RDAC register contents. The RDAC register acts as a scratchpad register, allowing as many value changes as necessary to place the potentiometer wiper in the correct position. The RDAC register can be programmed with any position setting via the standard serial peripheral interface (SPI) by loading the 16-bit data-word.
WRITE PROTECTION
On power-up, the serial data input register write command for the RDAC register is disabled. The RDAC write protect bit, C1 of the control register (see Table 9 and Table 10), is set to 0 by default. This disables any change of the RDAC register content, regardless of the software commands, except that the RDAC register can be refreshed to midscale using the software reset command (Command 3, see Table 8) or through hardware, using the RESET pin. To enable programming of the variable resistor wiper position (programming the RDAC register), the write protect bit, C1 of the control register, must first be programmed. This is accomplished by loading the serial data input register with Command 4 (see Table 8).
SERIAL DATA INTERFACE
The AD5293 contains a serial interface (SYNC, SCLK, DIN, and SDO) that is compatible with SPI standards, as well as most DSPs. The device allows data to be written to every register via the SPI.
BASIC OPERATION
The basic mode of setting the variable resistor wiper position (programming the RDAC register) is accomplished by loading the serial data input register with Command 1 (see Table 8) and the desired wiper position data. The RDY pin can be used to monitor the completion of this RDAC register write command. Command 2 can be used to read back the contents of the RDAC register (see Table 8). After issuing the readback command, the RDY pin can be monitored to indicate when the data is available to be read out on SDO in the next SPI operation. Instead of monitoring the RDY pin, a minimum delay can be implemented when executing a write or read command (see Table 3). Table 7 provides an example listing of a sequence of serial data input (DIN) words with the serial data output appearing at the SDO pin in hexadecimal format for an RDAC write and read. Table 7. RDAC Register Write and Read Example
DIN 0x1802 0x0500 0x0800 0x0000 SDO 0xXXXX1 0x1802 0x0500 0x0100 Action Enable update of wiper position. Write 0x100 to the RDAC register. Wiper moves to 1/4 full-scale position. Prepare data read from RDAC register. NOP (Instruction 0) sends a 16-bit word out of SDO, where the last 10 bits contain the contents of the RDAC register.
SHIFT REGISTER
The AD5293 shift register is 16 bits wide (see Figure 2). The 16-bit data-word consists of two unused bits, which are set to 0, followed by four control bits and 10 RDAC data bits. Data is loaded MSB first (Bit DB15). The four control bits determine the function of the software command (see Table 8). Figure 3 shows a timing diagram of a typical write sequence. The write sequence begins by bringing the SYNC line low. The SYNC pin must be held low until the complete data-word is loaded from the DIN pin. When SYNC returns high, the serial data-word is decoded according to the instructions in Table 8. The command bits (Cx) control the operation of the digital potentiometer. The data bits (Dx) are the values that are loaded into the decoded register. The AD5293 has an internal counter that counts a multiple of 16 bits (per frame) for proper operation. For example, the AD5293 works with a 32-bit word, but it cannot work properly with a 31- or 33-bit word. The AD5293 does not require a continuous SCLK, when SYNC is high, and all interface pins should be operated close to the supply rails to minimize power consumption in the digital input buffers.
RDAC REGISTER
The RDAC register directly controls the position of the digital potentiometer wiper. For example, when the RDAC register is loaded with all 0s, the wiper is connected to Terminal B of the variable resistor. The RDAC register is a standard logic register; there is no restriction on the number of changes allowed. The RDY pin can be used to monitor the completion of a write to or read from the RDAC register. The AD5293 presets to mid-scale on power-up.
1
X = unknown.
SHUTDOWN MODE
The AD5293 can be placed in shutdown mode by executing the software shutdown command (see Command 6 in Table 8) and then setting the LSB to 1. This feature places the RDAC in a special state in which Terminal A is open-circuited and Wiper W is connected to Terminal B. The contents of the RDAC register are unchanged by entering shutdown mode. However, all commands listed in Table 8 are supported while in shutdown mode.
Rev. 0 | Page 14 of 20
AD5293
RESET
A low-to-high transition of the hardware RESET pin loads the RDAC register with midscale. The AD5293 can also be reset through software by executing Command 3 (see Table 8). The control register is restored with default settings (see Table 10). The SDO pin contains an open-drain N-channel FET that requires a pull-up resistor, if this function is used. As shown in Figure 32, the SDO pin of one package must be tied to the DIN pin of the next package. Users may need to increase the clock period because the pull-up resistor and the capacitive loading at the SDO/DIN interface may require an additional time delay between subsequent devices. When two AD5293 devices are daisy-chained, 32 bits of data are required. The first 16 bits go to U2, and the second 16 bits go to U1. The SYNC pin should be held low until all 32 bits are clocked into their respective serial registers. The SYNC pin is then pulled high to complete the operation.
VLOGIC
RESISTOR PERFORMANCE MODE
This mode activates a new, patented 1% end-to-end resistor tolerance that ensures a 1% resistor tolerance on each code, that is, code = half scale, RWB = 10 k 100 . See Table 2 to verify which codes achieve 1% resistor tolerance. The resistor performance mode is activated by programming Bit C2 of the control register (see Table 9 and Table 10). The typical settling time is shown in Figure 23.
DAISY-CHAIN OPERATION
The serial data output pin (SDO) serves two purposes. It can be used to read the contents of the wiper setting, using Command 2 (see Table 8), or it can be used for daisy-chaining multiple devices. The remaining instructions are valid for daisy-chaining multiple devices in simultaneous operations. Daisy chaining minimizes the number of port pins required from the controlling IC. Table 8. Command Operation Truth Table
Command 0 1 2 3 4 5 6 Command Bits[B13:B10] C3 C2 C1 C0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 1 1 0 1 0 1 1 0 0 0 0 1 0 D9 X D9 X X X X X D8 X D8 X X X X X D7 X D7 X X X X X Data Bits[B9:B0] 1 D6 D5 D4 D3 X X X X D6 D5 D4 D3 X X X X X X X X X X X X X X X X X X X X D2 X D2 X X D2 X X D1 X D1 X X D1 X X
MOSI MICROCONTROLLER SCLK SS DIN
AD5293
U1 SDO
RP 2.2k DIN
AD5293
U2 SDO
SYNC
SCLK
SYNC
SCLK
07675-039
Figure 32. Daisy-Chain Configuration Using SDO
D0 X D0 X X X X D0
Operation NOP command. Do nothing. Write contents of serial register data to RDAC. Read RDAC wiper setting from SDO output in the next frame. Reset. Refresh RDAC with midscale code. Write contents of serial register data to control register. Read control register from SDO output in the next frame. Software power-down. D0 = 0 (normal mode). D0 = 1 (device placed in shutdown mode).
1
X = don't care.
Table 9. Control Register Bit Map
D9 X1
1
D8 X1
D7 X1
D6 X1
D5 X1
D4 X1
D3 X1
D2 C2
D1 C1
D0 X1
X = don't care.
Table 10. Control Register Bit Descriptions
Register Name Control Bit Name C2 Description Calibration enable. 0 = Resistor Performance Mode (default). 1 = Normal Mode. RDAC register write protect. 0 = locks the wiper position through the digital interface (default). 1 = allows update of wiper position through digital interface.
Rev. 0 | Page 15 of 20
C1
AD5293
RDAC ARCHITECTURE
To achieve optimum cost performance, Analog Devices, Inc., has patented the RDAC segmentation architecture for all the digital potentiometers. In particular, the AD5293 employs a three-stage segmentation approach, as shown in Figure 33. The AD5293 wiper switch is designed with transmission gate CMOS topology and with the gate voltage derived from VDD.
A
The digitally programmed output resistance between the W terminal and the A terminal, RWA, and the W terminal and B terminal, RWB, is calibrated to give a maximum of 1% absolute resistance error over both the full supply and temperature ranges. As a result, the general equation for determining the digitally programmed output resistance between the W terminal and B terminal is D (1) RWB (D ) = x R AB 1024
RL
RL
RM
where: D is the decimal equivalent of the binary code loaded in the 10-bit RDAC register. RAB is the end-to-end resistance.
SW RW W
RM
10-BIT ADDRESS DECODER RL
RW RM
Similar to the mechanical potentiometer, the resistance of the RDAC between the W terminal and the A terminal also produces a digitally controlled complementary resistance, RWA. RWA is also calibrated to give a maximum of 1% absolute resistance error. RWA starts at the maximum resistance value and decreases as the data loaded into the latch increases. The general equation for this operation is
RWA (D) =
RM RL
1024 - D x R AB 1024
(2)
B
07675-040
where: D is the decimal equivalent of the binary code loaded in the 10-bit RDAC register. RAB is the end-to-end resistance. In the zero-scale condition, a finite total wiper resistance of 120 is present. Regardless of the setting in which the part is operating, care should be taken to limit the current between the A terminal and B terminal, the W terminal and A terminal, and the W terminal and B terminal to the maximum continuous current of 3 mA or to the pulse current specified in Table 4. Otherwise, degradation, or possible destruction of the internal switch contact, can occur.
Figure 33. Simplified RDAC Circuit
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation--1% Resistor Tolerance
The AD5293 operates in rheostat mode when only two terminals are used as a variable resistor. The unused terminal can be left floating or can be tied to the W terminal as shown in Figure 34.
A W B B A W B A W
07675-041
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at the wiper-to-B terminal and the wiper-to-A terminal that is proportional to the input voltage at A to B, as shown in Figure 35. Unlike the polarity of VDD to GND, which must be positive, voltage across A to B, W to A, and W to B can be at either polarity.
VIN A W B VOUT
07675-042
Figure 34. Rheostat Mode Configuration
The nominal resistance between Terminal A and Terminal B, RAB, is available in 20 k and has 1024 tap points that are accessed by the wiper terminal. The 10-bit data in the RDAC latch is decoded to select one of the 1024 possible wiper settings. The AD5293 contains an internal 1% resistor tolerance calibration feature that can be enabled or disabled (enabled by default) by programming Bit C2 of the control register (see Table 9 and Table 10).
Figure 35. Potentiometer Mode Configuration
Rev. 0 | Page 16 of 20
AD5293
If ignoring the effect of the wiper resistance for simplicity, connecting the A terminal to 30 V and the B terminal to ground produces an output voltage at the Wiper W to Terminal B that ranges from 0 V to 30 V - 1 LSB. Each LSB of voltage is equal to the voltage applied across the A terminal and B terminal, divided by the 1024 positions of the potentiometer divider. The general equation defining the output voltage at VW, with respect to ground for any valid input voltage applied to Terminal A and Terminal B, is
VW (D) =
TERMINAL VOLTAGE OPERATING RANGE
The positive VDD and negative VSS power supplies of the AD5293 define the boundary conditions for proper 3-terminal, digital potentiometer operation. Supply signals present on the A, B, and W terminals that exceed VDD or VSS are clamped by the internal forward-biased diodes (see Figure 37).
VDD
1024 - D D xVA + xVB 1024 1024
(3)
A W B
To optimize the wiper position update rate when in voltage divider mode, it is recommended that the internal 1% resistor tolerance calibration feature be disabled by programming Bit C2 of the control register (see Table 9 and Table 10). Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike when the part is in the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors, RWA and RWB, not on the absolute values. Therefore, the temperature drift reduces to 5 ppm/C.
VSS
Figure 37. Maximum Terminal Voltages Set by VDD and VSS
EXT_CAP CAPACITOR
A 1 F capacitor to GND must be connected to the EXT_CAP pin (see Figure 36) on power-up and throughout the operation of the AD5293. This capacitor must have a voltage rating of 7 V.
AD5293
C1 1F EXT_CAP
The ground pin of the AD5293 is primarily used as a digital ground reference. To minimize the digital ground bounce, the AD5293 ground pin should be joined remotely to common ground. The digital input control signals to the AD5293 must be referenced to the device ground pin (GND) to satisfy the logic level defined in the Specifications section.
Power-Up Sequence
Because there are diodes to limit the voltage compliance at the A, B, and W terminals (see Figure 37), it is important to power VDD and VSS first, before applying any voltage to the A, B, and W terminals. Otherwise, the diode is forward-biased such that VDD and VSS are powered up unintentionally. The ideal power-up sequence is GND, VSS, VLOGIC, VDD, the digital inputs, and then VA, VB, and VW. The order of powering up VA, VB, VW, and the digital inputs is not important, as long as they are powered after VDD, VSS, and VLOGIC. Regardless of the power-up sequence and the ramp rates of the power supplies, the power-on preset activates after VLOGIC is powered, restoring midscale to the RDAC register.
GND
07675-043
Figure 36. Hardware Setup for the EXT_CAP Pin
Rev. 0 | Page 17 of 20
07675-044
AD5293 APPLICATIONS INFORMATION
HIGH VOLTAGE DAC
The AD5293 can be configured as a high voltage DAC, with output voltage as high as 33 V. The circuit is shown in Figure 38. The output is
VOUT (D) = D x 1.2 V x 1024 R 1 + 2 R1
HIGH ACCURACY DAC
It is possible to configure the AD5293 as a high accuracy DAC by optimizing the resolution of the device over a specific reduced voltage range. This is achieved by placing external resistors on either side of the RDAC, as shown in Figure 40. The improved 1% resistor tolerance specification greatly reduces errors that are associated with matching to discrete resistors.
VOUT (D) = R3 + (D 1024 x RAB ) xV DD R1 + ((1024 - D )1024) x RAB + R3
VDD
U2
(4)
where D is the decimal code from 0 to 1023.
VDD RBIAS VDD U1A V+ D1
(5)
ADR512
AD8512
V-
AD5293
20k B U1B VOUT
U1
R1 VDD U2 1% V+
AD5293
R2 20k B
07675-153
AD8512
OP1177
V-
VOUT
07675-154
R1
R2
R3
Figure 38. High Voltage DAC
Figure 40. Optimizing Resolution
PROGRAMMABLE VOLTAGE SOURCE WITH BOOSTED OUTPUT
For applications that require high current adjustments, such as a laser diode or tunable laser, a boosted voltage source can be considered (see Figure 39).
U3 2N7002 VIN VOUT CC W U2 RBIAS IL
07675-155
VARIABLE GAIN INSTRUMENTATION AMPLIFIER
The AD8221 in conjunction with the AD5293 and the ADG1207, as shown in Figure 41, make an excellent instrumentation amplifier for use in data acquisition systems. The data acquisition system is low distortion and low noise enable it to condition signals in front of a variety of ADCs.
ADG1207
+VIN1 +VIN4 -VIN1 -VIN4 VSS VDD
AD5293
U1
A
B
OP184
SIGNAL LD
AD5293
AD8221
VOUT
Figure 39. Programmable Boosted Voltage Source
In this circuit, the inverting input of the op amp forces VOUT to be equal to the wiper voltage set by the digital potentiometer. The load current is then delivered by the supply via the N-channel FET (U3). The N-channel FET power handling must be adequate to dissipate (VIN - VOUT) x IL power. This circuit can source a maximum of 100 mA with a 33 V supply.
Figure 41. Data Acquisition System
The gain can be calculated by using Equation 6, as follows:
G(D) = 1 + 49.4 k (D 1024) x R AB
(6)
Rev. 0 | Page 18 of 20
07675-156
AD5293
AUDIO VOLUME CONTROL
The excellent THD performance and high voltage capability of the AD5293 make it ideal for digital volume control. The AD5293 is used as an audio attenuator; it can be connected directly to a gain amplifier. A large step change in the volume level at any arbitrary time can lead to an abrupt discontinuity of the audio signal, causing an audible zipper noise. To prevent this, a zero-crossing window detector can be inserted to the SYNC line to delay the device update until the audio signal crosses the window. Because the input signal can operate on top of any dc level, rather than absolute 0 V level, zero crossing in this case means the signal is ac-coupled, and the dc offset level is the signal zero reference point. The configuration to reduce zipper noise is shown in Figure 42, and the results of using this configuration are shown in Figure 43.
C1 VIN 1F 5V R1 100k +5V U2 VCC ADCMP371 GND U4B +5V R5 10k U3 VCC ADCMP371 GND R3 100k
4 5
The input is ac-coupled by C1 and attenuated down before feeding into the window comparator formed by U2, U3, and U4B. U6 is used to establish the signal as zero reference. The upper limit of the comparator is set above its offset and, therefore, the output pulses high whenever the input falls between 2.502 V and 2.497 V (or a 0.005 V window) in this example. This output is AND'ed with the chip select signal such that the AD5293 updates whenever the signal crosses the window. To avoid a constant update of the device, the chip select signal should be programmed as two pulses, rather than as one. In Figure 43, the lower trace shows that the volume level changes from a quarter-scale to full-scale when a signal change occurs near the zero-crossing window.
+15V C3 0.1F C2 0.1F -15V U4A 61
2
U1 VDD
AD5293
A
R4 90k
R2 200
+15V VSS W 20k SYNC SCLK DIN B GND
07675-157
U5 V+ V-
7408
VOUT
7408 SCLK DIN
5V
U6 V+ AD8541 V-
-15V
SYNC
Figure 42. Audio Volume Control with Zipper Noise Reduction
1
2
CHANNEL 1 FREQ = 20.25kHz 1.03V p-p
07675-158
Figure 43. Zipper Noise Detector
Rev. 0 | Page 19 of 20
AD5293 OUTLINE DIMENSIONS
5.10 5.00 4.90
14 8
4.50 4.40 4.30
1 7
6.40 BSC
PIN 1 0.65 BSC 1.05 1.00 0.80 0.15 0.05 COPLANARITY 0.10 1.20 MAX 0.20 0.09 8 0
0.30 0.19
SEATING PLANE
0.75 0.60 0.45
061908-A
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 44. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters
ORDERING GUIDE
Model AD5293BRUZ-20 1 AD5293BRUZ-20-RL71
1
RAB (k) 20 20
Resolution 1,024 1,024
Temperature Range -40C to +105C -40C to +105C
Package Description 14-Lead TSSOP 14-Lead TSSOP
Package Option RU-14 RU-14
Z = RoHS Compliant Part.
(c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07675-0-4/09(0)
Rev. 0 | Page 20 of 20

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